The Power of Assertions in SystemVerilog by Eduard Cerny Surrendra Dudani John Havlicek & Dmitry Korchemny

The Power of Assertions in SystemVerilog by Eduard Cerny Surrendra Dudani John Havlicek & Dmitry Korchemny

Author:Eduard Cerny, Surrendra Dudani, John Havlicek & Dmitry Korchemny
Language: eng
Format: epub
Publisher: Springer US, Boston, MA


Most property operators have both weak and strong versions, such as until and s_until . However, the unbounded operator always has only a weak form, and the unbounded operator s_eventually has only a strong form. When we say that eventually a happens, our intent is that a happens in some clock tick, and therefore the clock cannot stop ticking before a has been detected. When we say that a always happens, our intent is that a happens at each clock tick. If there are no clock ticks, the value of a is not checked. Therefore, in this case there is no requirement that the clock ticks.



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